Encasing arrangement for a semiconductor component

ABSTRACT

A semiconductor component package configuration includes a semiconductor chip mounted to a printed circuit board, and a substrate arranged between the semiconductor chip and the printed circuit board. The substrate is for routing the wiring terminals of the semiconductor chip to the printed circuit board. The substrate is connected to the printed circuit board by solder joints. A filler between the semiconductor chip and the substrate mechanically isolates the semiconductor chip and the solder joints. A metal layer, which is connected to solder joints, is applied to the substrate. At least one molded element of heat-dissipating material is applied to the metal layer and is connected in a heat-conducting manner to the metal layer. This provides the package configuration with an improved capability of conducting the lost power that is dissipated from the installed semiconductor chip, and the desired mechanical properties of the package arrangement are retained.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a semiconductor component packageconfiguration which includes a printed circuit board, a semiconductorchip and a substrate lying in between for routing the wiring terminalsof the semiconductor chip to the printed circuit board. The substrate isbonded to the printed circuit board by solder joints and the solderjoints are mechanically isolated from the semiconductor chip by afiller.

Integrated semiconductor circuits are used in various applications. Thesemiconductor chip is generally housed in a package and mounted on aprinted circuit board. For example, a semiconductor component can bearranged in a package arrangement according to what is known as an FBGApackage arrangement (FBGA: Fine Pitch Ball Grid Array), which is basedon what is known as the beam-lead bonding technique. This type ofpackage arrangement is characterized by a special package design withrespect to the arrangement of the solder balls.

A package arrangement such as the FBGA package arrangement, alsoreferred to as an FBGA package, usually includes a semiconductor chipwith terminals for electrically connecting to terminals of the printedcircuit board and a substrate that acts as a kind of wiring plane. Thesubstrate is in this case arranged between the semiconductor chip andthe printed circuit board. The substrate, as a wiring plane, haselectrically conducting connections to the terminals of thesemiconductor chip. These interconnects of the substrate are connectedin turn to the printed circuit board by solder joints. Since thesemiconductor chip and the solder joints or solder balls generally havedifferent coefficients of expansion under changing temperatures, it isnecessary for the semiconductor chip and the solder balls to bemechanically isolated from one another. For this purpose, a filler, alsoreferred to as an encapsulate or cushioning material, is provided, forexample, between the semiconductor chip and the substrate.

During the operation of an integrated semiconductor circuit there isgenerally a certain loss of power, which, to avoid potential damage, forexample, from overheating or accelerated aging, must be dissipated. Toeliminate the possibility of overheating a semiconductor component, itis provided with heat sinks or heat spreaders. Heat sinks are usuallycooled externally and consequently assume a constant temperature. Heatspreaders are used, for example, to create a larger surface area, whichbetter dissipates the heat to the outside by convection. They areformed, for example, by metal plates that are fastened on the package orintroduced directly into the package.

U.S. Pat. No. 5,814,894 shows a semiconductor component in which blindleads, which are connected to the chip and lead to contact bumps, areprovided for heat dissipation. However, only little heat can bedissipated in this way, and a heat sink is additionally provided.Problems also arise because of the different coefficients of expansion,since the arrangement is formed without any filling material.

The main heat path in the case of the described type of packagearrangements for dissipating the lost power is the path from thesemiconductor chip via the filling material and the solder balls to theprinted circuit board. The relatively poor thermal conductivity of thefilling material or the cushioning material in this case limits the heatresistance of the package. With limited thermal conductivity of thepackage, the lost power that can be dissipated is limited, as a resultof which the performance of an integrated semiconductor circuit maylikewise be limited.

A semiconductor component with such a filling material is presented, forexample, in U.S. Pat. No. 5,843,810, where the space between thesemiconductor chip and the wiring elements is filled with a buffermaterial that is in contact, via a seal, with an outer ring serving asreinforcement. The reference does not concern itself with the problem ofhow the lost heat of the chip will be dissipated.

An improvement in the thermal conductivity of the main heat path ispossible by using thermally conductive filling material or cushioningmaterial. However, there are limits to this method, since with thethermally conductive filler, the elastic properties and the desiredprocessing properties of the filling material are generally lost. Thishas the consequence of reduced mechanical isolation of the semiconductorchip and the solder balls.

SUMMARY OF THE INVENTION

The object of the present invention is to specify an arrangement of asemiconductor component in the described package arrangement which hasimproved conductivity of the lost power that will be dissipated from aninstalled semiconductor chip and with which the mechanical properties ofthe package arrangement are retained.

The object of the invention is obtained by providing a semiconductorcomponent package configuration including:

-   -   a semiconductor chip with wiring terminals; a printed circuit        board, on which the semiconductor component is mounted;    -   a substrate, which is arranged between the semiconductor chip        and the printed circuit board, for routing the wiring terminals        of the semiconductor chip to the printed circuit board;    -   in which the substrate is connected to the printed circuit board        by solder joints;    -   in which a filler is arranged between the semiconductor chip and        the substrate for mechanically isolating the semiconductor chip        and the solder joints;    -   in which there is applied to the substrate, a metal layer, which        is connected to at least one of the solder joints; and    -   in which at least one molded element of heat-dissipating        material is applied to the metal layer;    -   in which the molded element is connected in a heat-conducting        manner to the metal layer;    -   and in which the molded element of heat-dissipating material is        not in direct contact with the semiconductor chip.

The arrangement has a semiconductor chip with wiring terminals, aprinted circuit board, onto which the semiconductor component ismounted, and a substrate that is arranged between the semiconductor chipand the printed circuit board. The substrate serves for routing thewiring terminals of the semiconductor chip to the printed circuit boardand is connected to the printed circuit board by solder joints. Arrangedbetween the semiconductor chip and the substrate is a filler, whichserves for mechanically isolating the semiconductor chip and the solderjoints. Also applied on the substrate, in addition to the interconnectsto the terminals of the semiconductor chip, is a metal layer that isconnected to at least one of the solder joints. Furthermore, at leastone molded element of heat-dissipating material is applied to the metallayer and is connected to it in a heat-conducting manner. The provisionof the heat-conducting molded element improves the capability ofconducting the lost power of the package arrangement to be dissipated.The previously used filling material with the desired properties may beused as the filler.

The molded element serves, for example, for reducing at certain points,the distance between the substrate, also referred to as the interposer,and the semiconductor chip, and consequently for bridging the relativelypoor thermal conductivity of the filling material. Similarly, a furtherpossible heat path can be created by an appropriate locationalarrangement of the molded element, contributing to the removal of theproduced lost power. The transported heat is transferred to the metallayer of the substrate and conducted from it via the solder joints intothe metal areas of the printed circuit board. Accordingly, theheat-dissipating molded element performs the function of a heat sinkwith respect to the semiconductor chip. So that the mechanicalproperties of the package arrangement are not influenced by the moldedelement, the molded element is not in direct contact with thesemiconductor chip. The described structure of the package arrangementis used, in particular, in the case of FBGA package arrangements.

To shorten the distance between the substrate and the semiconductorchip, the molded element is arranged in a suitable way such that itprotrudes into the filler. The molded element is in this case preferablydesigned as a cylinder.

In the interests of high thermal conductivity, it is favorable for ametal layer to be applied to the substrate in the form of largeinterconnected metal areas. Similarly, the thermal conductivity and itsdistribution are enhanced by applying a plurality of relatively smallcylinders to the metal layer. Since metal has good thermal conductivity,the molded elements are preferably formed from metal.

The described structure of the metal layer and the molded elements canbe produced, for example, by a mask etching process or byelectrodepositing the molded elements. The molded elements or cylindersare embedded into the filling material before mounting the semiconductorchip. In the mounted state, the molded elements or cylinders protrude asfar as the chip surface, so that an improved heat path is produced fromthe semiconductor chip through the molded elements into the metal layer.From the metal layer, the heat is dissipated through solder joints orsolder balls that are not electrically connected and that are referredto as no-connects, and by thermal vias in the printed circuit board intometal tracks of the printed circuit board. These thermal vias are, forexample, metal-filled holes in the printed circuit board (board), whichcan be produced by known processes, for example by electrodeposition. Ifthe molded elements are arranged on the substrate in an appropriatenumber and with appropriate area coverage, a significant improvement inthe heat resistance is achieved, while at the same time retaining theelastic and isolating properties of the filling material.

A further refinement of the invention provides a molded element appliedto the metal layer and arranged on a side of the substrate facing thesemiconductor chip and to the side of the semiconductor chip. This opensa further heat path to the side of the semiconductor chip, whichaltogether increases the thermal conductivity of the FBGA packagearrangement.

The mechanical stability of the described package arrangement can beincreased by what is known as a support ring, i.e. a frame whichsurrounds the semiconductor chip. An application of this type isexpedient, for example, for package arrangements in which the array ofsolder joints or the interposer extends out over the area of the chip(“fan out”). The arrangement of this frame as specified by the inventionconsequently provides it with the function of a heat sink in addition tothe mechanically stabilizing function.

If, in addition, the frame is electrically conductive and connected toground potential, additional electrical improvements are obtained. Theframe, which has, with respect to the housing, the form of a ringantenna, produces a general shielding of all of the electrical paths ofthe metal layer. In addition, the inductance of the ground terminalsconnected to the frame is decreased, which reduces, in particular, thenoise caused by rapid changes in current (“delta I noise”). At the sametime, the capacitance of the ground terminals is increased, which leadsto better radio frequency decoupling of the voltage supply system. Theinductance of further electrical connections, for example, of data linesor address lines, is likewise lowered by the additional ground referencethat the frame represents.

In a development of the invention, the frame is applied directly to themetal layer and is fastened by a heat-conducting adhesive. If the metallayer is located on a side of the substrate lying opposite from theframe, the frame is applied to the metal layer and connected to it in aheat-conducting manner through a clearance in the substrate by using aconducting adhesive layer. This connection may also be performed bybonding.

To improve the heat dissipation via the frame, in a development of theinvention, an additional, electrically non-conducting, thermallyconductive connection is arranged between the semiconductor chip and themolded element. This thermally conductive connection may be established,for example, by a heat-conducting paste.

Moreover, further improved heat dissipation from the semiconductor chipcan be achieved by connecting wiring terminals of the semiconductorchip, which have no electrical function, to the metal layer of theinterposer.

The invention is explained in more detail below on the basis of thefigures represented in the drawing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 are cross sectional views of an embodiment of theinvention;

FIG. 3 is a plan view of an embodiment of the invention;

FIG. 4 is a three-dimensional representation of an embodiment of theinvention;

FIG. 5 is a sectional view of an embodiment of a package arrangement;

FIGS. 6 and 7 show details from FIG. 5; and

FIG. 8 is a plan view of the embodiment of the invention shown in FIG.5.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a cross section of an embodiment of the inventionconstructed as an FBGA package arrangement, before mounting thesemiconductor chip. It shows the substrate 3 (interposer), to which ametal layer 5 is applied. The metal layer 5 has a molded element 7 ofheat-dissipating material, which is designed in FIG. 1 as a cylinder.Shown alongside the cylinder are further identical cylinders that are,for example, formed from metal, and that are connected in aheat-conducting manner to the metal layer. Applied above the metal layer5 is the filler 4 (cushioning material).

FIG. 2 shows a cross section of the structure shown in FIG. 1 aftermounting the chip and solder balls and after being soldered onto theprinted circuit board 8. The substrate 3 is arranged between thesemiconductor chip 2 and the printed circuit board 8 and serves forrouting wiring terminals (known as bonding pads) of the semiconductorchip 2 to the printed circuit board 8 by using the interconnect 13. Thesubstrate 3 is connected to the printed circuit board 8 by solder joints6. The filler 4 is arranged between the semiconductor chip 2 and thesubstrate 3 and serves for mechanically isolating the semiconductor chip2 and the solder joints 6. The printed circuit board 8 is made up of thePCB 81 itself and a copper layer 82 of a larger surface area (powerplane of the PCB). After the semiconductor chip 2 has been laminated on,a comparatively small distance 10 is obtained between the semiconductorchip 2 and the molded elements 7. This distance is determinedessentially by the technical aspects of the process and is, for example,10–20 μm. The filler 4 usually consists of a polyimide-based material.The substrate 3 consists, for example, of a supporting material FR-4.The lost power generated in the semiconductor chip 2 is dissipated viathe metal layer 5 and the solder joints 6 by way of the representedthermal via 9 into the printed circuit board 8, represented by theheat-conducting path 20. Since, over the molded element 7, the distancebetween the metal layer 5 and the semiconductor chip 2 is reduced, thethermal conductivity along the heat-conducting path 20, and consequentlyof the semiconductor component 1 as a whole, is increased.

FIGS. 3 and 4 respectively show a plan view and a three-dimensionalrepresentation of the embodiment of the invention shown in FIGS. 1 and2. The wiring terminals 11 of the semiconductor chip 2 are connected tothe solder joints or solder balls 6 by the terminals 61 for the solderjoints. The terminals 62 designate terminals for“thermal”, i.e.electrically inactive, solder joints 6. The metal layer 5 is arranged inthe form of large interconnected metal areas. The molded elements 7 areapplied to the metal layer 5 in a correspondingly dense coverage of thesurface.

FIG. 5 shows a sectional representation of further package arrangement.According to a further embodiment of the invention, the molded element 7is arranged on the side of the substrate 5 facing the semiconductor chip2 and to the side of the semiconductor chip 2. The molded element 7 isdesigned in the form of a frame which surrounds the semiconductor chip2. The frame also contributes to the mechanical stabilization of thepackage.

The sectional representation shown in FIG. 5 is respectively representedas a detail in FIGS. 6 and 7. The molded element 7 is applied to themetal layer 5 for example by a heat-conducting adhesive. In thisexemplary embodiment, a plurality of nubbins 14 are arranged between thesemiconductor chip 2 and the substrate 3. The nubbins 14 consist, forexample, of an organic material containing silicone rubber. The moldedelement 7 or the frame is expediently formed from metal. To improve thethermal conductivity between the semiconductor chip 2 and the moldedelement 7, an additional thermally conductive connection 15 is arrangedbetween the semiconductor chip 2 and the molded element 7, for example,in the form of a heat-conducting paste, as represented in FIG. 7. Theadhesive layer, not represented in FIG. 6 or FIG. 7, may also bereplaced by a bonding. The metal layer 5 is formed here, as in theexemplary embodiments previously described, for example, from copper.

FIG. 8 shows a plan view of the embodiment of the invention shown inFIG. 5 with interconnects 13 and the wiring terminals 11. The metallayer 5 is arranged in the form of interconnected metal areas. For theconnection of the molded element or the frame to ground potential, themetal layer 5 is correspondingly connected by solder balls (notrepresented in the FIG.) to ground terminals (known as ground pins).

1. A semiconductor component package configuration, comprising: asemiconductor chip having wiring terminals; a printed circuit boardhaving said semiconductor component mounted thereon; a substrateconfigured between said semiconductor chip and said printed circuitboard, said substrate for routing said wiring terminals of saidsemiconductor chip to said printed circuit board; solder jointsconnecting said substrate to said printed circuit board; a fillerconfigured between said semiconductor chip and said substrate, saidfiller for mechanically isolating said semiconductor chip and saidsoldered joints; a metal layer applied to said substrate, said metallayer being connected to at least one of said solder joints; and atleast one molded element of heat-dissipating material applied to saidmetal layer, said molded element connected in a heat-conducting mannerto said metal layer, said molded element not directly contacting saidsemiconductor chip.
 2. The configuration according to claim 1, wherein:said molded element is configured between said substrate and saidsemiconductor chip and protrudes into said filler; and said moldedelement is at a distance of about 10–20 μm from said semiconductor chip.3. The configuration according to claim 2, wherein: said molded elementis formed as a cylinder.
 4. The configuration according to claim 1,wherein: said molded element is formed from metal.
 5. The configurationaccording to claim 4, wherein: said molded element has beenelectrodeposited onto said metal layer.
 6. The configuration accordingto claim 4, wherein: said molded element has been applied to said metallayer by a mask etching process.
 7. The configuration according to claim1, wherein: said substrate has a side facing said semiconductor chip;said semiconductor chip has a side; and said molded element isconfigured on said side of said substrate facing said semiconductor chipand to said side of said semiconductor chip.
 8. The configurationaccording to claim 7, wherein: said molded element is formed as anelectrically conductive, metallic frame surrounding said semiconductorchip; and said molded element is connected to ground potential.
 9. Theconfiguration according to claim 7, comprising: a heat-conductingadhesive connecting said molded element to said metal layer.
 10. Theconfiguration according to claim 7, wherein: said molded element isbonded to said metal layer.
 11. The configuration according to claim 7,comprising: an additional, electrically non-conducting, thermallyconductive connection configured between said semiconductor chip andsaid molded element.